One embodiment of the present invention relates to a memory cell with a gated fuse element. More specifically, one embodiment of the present invention relates to a one time programmable memory cell with thin gate-ox fuse elements.
There are two main types of memory cells or devices used in the field of data storage. The first type is volatile memory that has the information stored in a particular memory cell, where the information is lost the instant power is removed. The second type is a non-volatile memory cell in which the information is preserved even with the power removed. Of the second type, some designs provide for multiple programming while other designs provide for one-time programming. Typically, the manufacturing techniques used to form such non-volatile memories are quite different from a standard logic processes, thereby dramatically increasing the complexity and chip size of such memories.
One-time programmable memory cells or devices have numerous applications, specifically long-term applications. For example, one-time programmable memory cells may be used in post package programming to install security codes, keys or identifiers. These codes, keys or identifiers cannot be electrically altered or decoded without destroying the circuitry. Further, such one-time programmable memory cells or devices may be used to make a device unique for a specific application. Alternatively, such memory cells or devices may be used as memory elements in programmable logic and read only memory devices.
One known one-time programmable memory cell uses storage elements combined with poly fuses. Poly fuses in general are resistors that require a great deal of current, on the order of many milliamps, to set the state of (i.e., “blow”) the fuse. Building a memory device array using such poly fuse elements requires adding a switch to the array, used to switch the current through the selected fuse to be blown. Adding such a switch to a memory cell adds to the overall size of the memory cell, increasing manufacturing cost.
Another limitation associated with a poly fuse is that the resistance ratio of the poly fuse is fairly close together, having only about one order of magnitude difference in value. In other words, the resistance of poly fuses before the blow and the resistance after the blow is fairly close. Therefore, sensing the difference between a blown and un-blown poly fuse is difficult, requiring the addition of a very large operational amplifier into the circuit to sense the state of the fuses. Adding such an operational amplifier to a memory cell adds to the overall size of the memory cell, increasing manufacturing cost.
Further, it is difficult to control the programmed state resistance of the poly fuses. For example, one conventional programmed poly fuse may have a resistance of a few kilo ohms, while a neighboring poly fuse in the same memory cell array may have a resistance in the range of 10 to 100 kilo ohms.
Yet another limitation of the conventional poly fuses is the instability of their programmed state resistance. Specifically, the resistance of the programmed poly fuses tends to increase over time. In the worst case, the programmed poly fuse may actually switch from the programmed state to an unprogrammed state resulting in circuit failure.
CMOS technology is the integration of both NMOS and PMOS transistors on a silicon substrate. The NMOS transistor consists of a N-type doped polysilicon gate, a channel conduction region, and source/drain regions formed by diffusion of N-type dopant in the silicon substrate. The channel region separates the source from the drain in the lateral direction, whereas a layer of dielectric material that prevents electrical current flow separates the polysilicon gate from the channel. Similarly, the PMOS transistor architecture is the same as the NMOS transistor provided previously but using a P-type dopant.
The dielectric material separating the polysilicon gate from the channel region usually consists of thermally grown silicon dioxide (SiO2) material (referred to as the gate oxide or oxide) that leaks very little current through a mechanism called Fowler-Nordheim tunneling under voltage stress. When the transistor is stressed beyond a critical electrical field (applied voltage divided by the thickness of the oxide) the oxide ruptures, destroying (referred to as “blowing”) the transistor.
Thin gate oxides allow direct tunneling current to behave quite differently than thicker oxides that exhibit Fowler-Nordheim tunneling. Rupturing the thin oxide requires consideration for pulse width duration and amplitude to limit power through the gate oxide to produce reliable, low resistance gate-ox fuse transistors.
Rupturing the gate oxide is one technique used to program a non-volatile memory array. U.S. Pat. No. 6,044,012 discloses a technique for rupturing the gate oxide of a transistor. But here the oxide is about 40 to 70 Å thick. The probability of direct tunneling, rather than Fowler-Nordheim tunneling, of gate current through an oxide of this thickness is extremely low. Furthermore, the voltage required to rupture this thick oxide is substantially high and requires using a charge pump circuit. The '012 patent does not disclose a final programmed resistance, but is believed to be in the high kilo ohms range.
U.S. Pat. No. 5,886,392 discloses a one-time programmable element having a controlled programmed state resistance with multiple fuses. Both the final resistance values are in the high kilo ohms range and the spread of these values is wide as well. Again, a complicated circuit would have to be designed if the final resistance is not within a tight range. Adding more fuses may lower the resistance but increases the die size.
Further limitations and disadvantages of conventional and traditional approaches will become apparent to one of skill in the art, through comparison of such systems with the present invention as set forth in the remainder of the present application with reference to the drawings.